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| CY7C1021DV33 1-Mbit (64K x 16) Static RAM Features * Temperature Ranges -- Industrial: -40C to 85C -- Automotive-A: -40C to 85C -- Automotive-E: -40C to 125C * Pin-and function-compatible with CY7C1021CV33 * High speed -- tAA = 10 ns * Low active power -- ICC = 60 mA @ 10 ns * Low CMOS standby power * * * * * -- ISB2 = 3 mA 2.0V data retention Automatic power-down when deselected CMOS for optimum speed/power Independent control of upper and lower bits Available in Pb-free 44-pin 400-Mil wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages Functional Description[1] The CY7C1021DV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the end of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages. Logic Block Diagram DATA IN DRIVERS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 64K x 16 RAM Array SENSE AMPS I/O0-I/O7 I/O8-I/O15 COLUMN DECODER BHE WE CE OE BLE Note 1. For guidelines on SRAM system design, please refer to the "System Design Guidelines" Cypress application note, available on the internet at www.cypress.com Cypress Semiconductor Corporation Document #: 38-05460 Rev. *D A8 A9 A10 A11 A12 A13 A14 A15 * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised November 8, 2006 [+] Feedback CY7C1021DV33 Selection Guide -10 (Industrial/Automotive-A) Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 60 3 -12 (Automotive-E)[2] 12 100 15 Unit ns mA mA Pin Configuration[3] SOJ/TSOP II Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE 48-ball VFBGA Top View 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 NC A15 A13 A10 5 A2 CE I/O2 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O1 VCC VSS I/O6 I/O7 NC A B C D E F G H BHE I/O 10 I/O 11 I/O12 I/O13 NC A8 Notes 2. Automotive product information is Preliminary. 3. NC pins are not connected on the die. Document #: 38-05460 Rev. *D Page 2 of 11 [+] Feedback CY7C1021DV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[4] .... -0.3V to +4.6V DC Voltage Applied to Outputs in High-Z State[4] ......................................-0.3V to VCC+0.3V DC Input Voltage[4] ...................................-0.3V to VCC+0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range Range Industrial Automotive-A Automotive-E Ambient Temperature -40C to +85C -40C to +85C -40C to +125C VCC 3.3V 0.3V Speed 10 ns 10 ns 12 ns DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[4] GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz ISB1 ISB2 Automatic CE Power-Down Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Current --TTL Inputs Automatic CE Power-Down Max. VCC, CE > VCC - 0.3V, Current --CMOS Inputs VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 -10 (Ind'l/Auto-A) Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 60 55 45 30 10 3 2.0 -0.3 -5 -5 Max. -12 (Auto-E) Min. 2.4 0.4 VCC + 0.3 0.8 +5 +5 100 90 60 50 15 Max. Unit V V V V A A mA mA mA mA mA mA Input Leakage Current Output Leakage Current VCC Operating Supply Current Capacitance[5] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF Thermal Resistance[5] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board SOJ 59.52 36.75 TSOP II VFBGA 53.91 21.24 36 9 Unit C/W C/W Notes 4. VIL (min.) = -2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05460 Rev. *D Page 3 of 11 [+] Feedback CY7C1021DV33 AC Test Loads and Waveforms[6] Z = 50 OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 3.0V 90% ALL INPUT PULSES 90% 10% 10% 30 pF* GND (a) Rise Time: 1 V/ns (b) Fall Time: 1 V/ns High-Z characteristics: R 317 3.3V OUTPUT 5 pF R2 351 (c) Note 6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05460 Rev. *D Page 4 of 11 [+] Feedback CY7C1021DV33 Switching Characteristics Over the Operating Range[7] -10 (Ind'l/Auto-A) Parameter Read Cycle tpower[8] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[11] tPD[11] tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Cycle[12] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to WE LOW to Low-Z[10] High-Z[9, 10] 7 10 8 8 0 0 7 5 0 3 5 8 12 9 9 0 0 8 6 0 3 6 ns ns ns ns ns ns ns ns ns ns ns VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to OE HIGH to CE LOW to CE HIGH to Low-Z[10] High-Z[9, 10] 3 5 0 10 5 0 6 0 6 0 12 6 High-Z[9, 10] Low-Z[10] 0 5 3 6 3 10 5 0 6 100 10 10 3 12 6 100 12 12 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. -12 (Auto-E) Min. Max. Unit CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z Byte Enable to End of Write Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 8. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. This parameter is guaranteed by design and is not tested. 12. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05460 Rev. *D Page 5 of 11 [+] Feedback CY7C1021DV33 Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[5] tR[13] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC - 0.3V, Industrial VIN > VCC - 0.3V or VIN < 0.3V Automotive 0 tRC Conditions Min. 2 3 15 Max. Unit V mA mA ns ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[14, 15] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE HIGH IMPEDANCE Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 38-05460 Rev. *D Page 6 of 11 [+] Feedback CY7C1021DV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[17, 18] tWC ADDRESS tSA CE tAW tSCE tHA tPWE WE tBW BHE, BLE tSD DATA I/O tHD Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tPWE WE tSCE CE tSD DATA I/O tHD tHA Notes 17. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05460 Rev. *D Page 7 of 11 [+] Feedback CY7C1021DV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tSA WE tBW BHE, BLE tPWE tHA tHZWE DATA I/O tSD tHD tLZWE Truth Table CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O0-I/O7 High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z High-Z I/O8-I/O15 High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z High-Z Power-down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1021DV33-10VXI CY7C1021DV33-10ZSXI CY7C1021DV33-10BVXI 10 12 CY7C1021DV33-10ZSXA CY7C1021DV33-12ZSXE Package Name 51-85082 51-85087 51-85150 51-85087 51-85087 Package Type 44-pin (400-Mil) Molded SOJ (Pb-free) 44-pin TSOP Type II (Pb-free) 48-ball VFBGA (Pb-free) 44-pin TSOP Type II (Pb-free) 44-pin TSOP Type II (Pb-free) Automotive-A Automotive-E Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05460 Rev. *D Page 8 of 11 [+] Feedback CY7C1021DV33 Package Diagrams Figure 1. 44-pin (400-Mil) Molded SOJ (51-85082) 51-85082-*B Figure 2. 44-pin Thin Small Outline Package Type II (51-85087) 51-85087-*A Document #: 38-05460 Rev. *D Page 9 of 11 [+] Feedback CY7C1021DV33 Package Diagrams (continued) Figure 3. 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.000.10 8.000.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 6.000.10 A 1.875 0.75 3.75 B 6.000.10 0.55 MAX. 0.25 C 0.15(4X) 0.210.05 0.10 C SEATING PLANE 0.26 MAX. C 1.00 MAX 51-85150-*D All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05460 Rev. *D Page 10 of 11 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1021DV33 Document History Page Document Title: CY7C1021DV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05460 REV. ** *A *B ECN NO. 201560 233693 263769 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Information data sheet for C9 IPP DC parameters are modified as per Eros (Spec # 01-02165). Pb-free Offering In Ordering Information Changed I/O1 - I/O16 to I/O0 - I/O15 Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information Reduced Speed bins to -8 and -10 ns Converted from Preliminary to Final Removed Commercial Operating range Removed 8 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Added Automotive Information Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #4 *C *D 307601 520652 See ECN See ECN RKF VKN Document #: 38-05460 Rev. *D Page 11 of 11 [+] Feedback |
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